(1) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method for forming contact holes in a semiconductor device.
(2) Description of the Related Art
A typical example of a conventional method for forming contact holes in a semiconductor device is first explained to assist the understanding of tile present invention. FIGS. 1A through 1C are cross-sectional elevated views of a conventional structure for explaining the process sequence employed in the fabrication of an n-channel MOS FET.
As shown in FIG. 1A, a p-type semiconductor substrate 21 is provided with n.sup.+ -type diffusion layers 22 serving as source/drain regions formed in a surface region thereof, a gate insulating film 24 formed on a surface of the semiconductor substrate 21, a gate electrode 25 formed on the gate insulating film 24, and a boron phosphosilicate glass (BPSG) insulating film 23a formed with BPSG deposited over the semiconductor substrate 21 by a chemical vapor deposition (CVD) technique. If the BPSG insulating film 23a thus formed is left as it is, a poor step coverage of Interconnect material results so that the BPSG insulating film 23a is subjected to a heating reflow process (hereinafter referred to as "reflow process") thereby forming a smoothed BPSG insulating film 23, as shown in FIG. 1B.
Next, after a lithography process is applied, a procedure for forming contact holes is carried out at desired positions of the BPSG insulating film 23. First, the BPSG insulating film 23 is subjected to an isotropic etching (wet-etching) using hydrofluoric acid thereby forming upper portions of the contact holes and then is subjected to an anisotropic etching using a reactive ion-etching (dry etching) technique thereby forming lower portions of the contact holes which extend to the surfaces of the n.sup.+ -diffusion layers 22 and the gate electrode 25, respectively. Further, in order to improve the step coverage of conductive interconnects, the edges 26 of contact holes are rounded by a reflow process, and after aluminum layers are deposited, the layers undergo a patterning process whereby the aluminum interconnects 28 are formed as shown in FIG. 1C.
In the conventional method for forming contact holes as explained above, the wet etching process and the contact hole reflow process are combined to improve the step coverage of conductive interconnects. However, although such a method has been confirmed to be effective for rounding the peripheral edges 26 of tile contact holes, the improvement in step coverage of tile conductive interconnects was shown to be only about 3% since the step coverage obtained by that method without any fellow process was about 10% while that obtained with the reflow process was about 13%. Consequently, for a deep contact hole such as the contact hole on the gate electrode 25, there is a possibility that the aluminum interconnect 28 may be fractured thereby giving a rise to serious reliability problems.
Problems in the conventional method explained above were that, with the deep contact holes formed for such electrodes as the gate electrodes 25, the conductive interconnects resulted in a poor step coverage and had a potential risk of being broken. Thus, conventionally, a method employed to improve the step coverage was to apply a reflow process to the edges 26 of the contact holes after the formation of tile contact holes. However, although this reflow process was effective for rounding the edges 26 of the contact holes, the step coverage improvement by this method alone was not sufficient since it was about 3% better than when the fellow process was not used. Also, in a structure such as a MOS memory device having a stacked capacitor cell, the arrangement was such that, in view of the structural nature, a storage capacitor is formed at an upper layer portion and a stacked electrode was made thick to ensure as large a storage capacity as possible. As a result, each of the interlayer insulating films unavoidably became thick so that the aspect ratio of the contact holes (ratio between the depth of a contact hole and the diameter of its bottom) was high and the step coverage of the contacts was poor, so that the contact reflow process alone was not sufficient for eliminating a risk of possible interconnect breakage. These problems in the conventional method are to be solved by the present invention.